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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) and femtocharge are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. high performance dual 14-bit, 125msps adc isla224p12 the isla224p12 is a high performance dual 14-bit 125msps analog-to-digital converter offeri ng very high dynamic range and low power consumption. it carries the export control classification number 3a991.c.3 and can be exported without a license to most countries, including china and russia. it is part of a pin-compatible family of 12- to 16-bit a/ds with maximum sample rates ranging from 125 to 500msps. this allows a design using the isla224p12 to accommodate any of the other pin-compatible a/ds with minimal changes. the isla224p12 is very flexible an d can be designed into a wide variety of systems. a se rial peripheral interf ace (spi) port allows access to its extensive configurabi lity as well as provides digital control over various analog para meters such as input gain and offset. digital output data is pr esented in selectable lvds or cmos formats in half-width, doub le data rate (ddr). operating from a 1.8v supply, performance is specified over the full industrial temp erature range (-40c to +85c). applications ? radar array processing ?software defined radio ? broadband communications ? high performance data acquisition ? communications test equipment features ? license-free import for most countries including china and russia (eccn 3a991.c.3) ?multi-adc support - spi programmable fine gain and offset control - multiple adc synchronization - optimized output timing ? clock duty cycle stabilizer ? nap and sleep modes ? programmable built-in test patterns ? ddr lvds-compatible or lvcmos outputs ? data output clock key specifications ? snr @ 125msps -74.7dbfs f in = 30mhz - 70.2dbfs f in = 363mhz ?sfdr @ 125msps - 86dbc f in = 30mhz - 79dbc f in = 363mhz ? total power consumption = 590mw digital error correction sha 1.25v vinbp vinbn 14-bit 125 msps adc clock management sha 14-bit 125 msps adc clkp clkn spi control vref clkoutp clkoutn d[13:0]p d[13:0]n orp orn outfmt outmode + ? vcm vref vinan vinap avdd clkdiv clkdivrstp clkdivrstn ovdd avss napslp resetn csb sclk sdio sdo ovss + - pin-compatible family model resolution speed (msps) isla224p25 14 250 isla224p20 14 200 isla224p13 14 130 isla222p25 12 250 isla222p20 12 200 isla222p13 12 130 august 17, 2012 fn7983.3
isla224p12 2 fn7983.3 august 17, 2012 pin configuration- lvds mode isla224p12 (72 ld qfn) top view avdd avdd avdd sdio 72 71 70 69 68 67 66 65 64 63 62 61 sclk csb sdo ovss orp orn ovdd ovss 60 59 d0p d0n d3p d3n d4p d4n d5p d5n clkoutp clkoutn rlvds ovss d6p d6n d7p d7n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dnc dnc napslp vcm avss vinbp vinbn avss avdd avdd avss vinan vinap avss 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avdd avdd avdd clkp clkn clkdivrstp clkdivrstn ovss ovdd d13n d13p d12n d12p ovdd 15 16 17 18 clkdiv dnc dnc resetn 33 34 35 36 d11n d11p d10n d10p d8p d8n d9p d9n 40 39 38 37 58 57 d1p d1n 56 55 d2p d2n connect thermal pad to avss thermal pad not drawn to scale. consult mechanical drawing for physical dimensions. pin descriptions - 72 ld qfn, lvds mode pin number lvds pin name lvds pin function 1, 2, 16, 17 dnc do not connect 9, 10, 19, 20, 21, 70, 71, 72 avdd 1.8v analog supply 5, 8, 11, 14 avss analog ground 27, 32, 62 ovdd 1.8v output supply 26, 45, 61, 65 ovss output ground 3 napslp tri-level power control (nap, sleep modes) 4 vcm common mode output 6, 7 vinbp, vinbn channel b analog input positive, negative
isla224p12 3 fn7983.3 august 17, 2012 12, 13 vinan, vinap channel a analog input negative, positive 15 clkdiv tri-level clock divider control 18 resetn power on reset (active low) 22, 23 clkp, clkn clock input true, complement 24, 25 clkdivrstp, clkdivrstn synchronous clock divider reset true, complement 28, 29 d13n, d13p lvds bit 13 (msb) output complement, true 30, 31 d12n, d12p lvds bit 12 output complement, true 33, 34 d11n, d11p lvds bit 11 output complement, true 35, 36 d10n, d10p lvds bit 10 output complement, true 37, 38 d9n, d9p lvds bit 9 output complement, true 39, 40 d8n, d8p lvds bit 8 output complement, true 41, 42 d7n, d7p lvds bit 7 output complement, true 43, 44 d6n, d6p lvds bit 6 output complement, true 46 rlvds lvds bias resistor (connect to ovss with 1%10k ) 47, 48 clkoutn, clkoutp lvds clock output complement, true 49, 50 d5n, d5p lvds bit 5 output complement, true 51, 52 d4n, d4p lvds bit 4 output complement, true 53, 54 d3n, d3p lvds bit 3 output complement, true 55, 56 d2n, d2p lvds bit 2 output complement, true 57, 58 d1n, d1p lvds bit 1 output complement, true 59, 60 d0n, d0p lvds bit 0 (lsb) output complement, true 63, 64 orn, orp lvds over range complement, true 66 sdo spi serial data output 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output exposed paddle avss analog ground pin descriptions - 72 ld qfn, lvds mode (continued) pin number lvds pin name lvds pin function
isla224p12 4 fn7983.3 august 17, 2012 pin configuration- cmos mode isla224p12 (72 ld qfn) top view avdd avdd avdd sdio 72 71 70 69 68 67 66 65 64 63 62 61 sclk csb sdo ovss or dnc ovdd ovss 60 59 d0 dnc d3 dnc d4 dnc d5 dnc clkout dnc rlvds ovss d6 dnc d7 dnc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dnc dnc napslp vcm avss vinbp vinbn avss avdd avdd avss vinan vinap avss 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avdd avdd avdd clkp clkn clkdivrstp clkdivrstn ovss ovdd dnc d13 dnc d12 ovdd 15 16 17 18 clkdiv dnc dnc resetn 33 34 35 36 dnc d11 dnc d10 d8 dnc d9 dnc 40 39 38 37 58 57 d1 dnc 56 55 d2 dnc connect thermal pad to avss thermal pad not drawn to scale. consult mechanical drawing for physical dimensions. pin descriptions - 72 ld qfn, cmos mode pin number cmos pin name cmos pin function 1, 2, 16, 17, 28, 30, 33, 35, 37, 39, 41, 43, 47, 49, 51, 53, 55, 57, 59, 63 dnc do not connect 9, 10, 19, 20, 21, 70, 71, 72 avdd 1.8v analog supply 5, 8, 11, 14 avss analog ground 27, 32, 62 ovdd 1.8v output supply 26, 45, 61, 65 ovss output ground 3 napslp tri-level power control (nap, sleep modes) 4 vcm common mode output
isla224p12 5 fn7983.3 august 17, 2012 6, 7 vinbp, vinbn channel b analog input positive, negative 12, 13 vinan, vinap channel a analog input negative, positive 15 clkdiv tri-level clock divider control 18 resetn power on reset (active low) 22, 23 clkp, clkn clock input true, complement 24, 25 clkdivrstp, clkdivrstn synchronous clock divider reset true, complement 29 d13 cmos bit 13 (msb) output 31 d12 cmos bit 12 output 34 d11 cmos bit 11 output 36 d10 cmos bit 10 output 38 d9 cmos bit 9 output 40 d8 cmos bit 8 output 42 d7 cmos bit 7 output 44 d6 cmos bit 6 output 46 rlvds lvds bias resistor (connect to ovss with 1%10k ) 48 clkout cmos clock output 50 d5 cmos bit 5 output 52 d4 cmos bit 4 output 54 d3 cmos bit 3 output 56 d2 cmos bit 2 output 58 d1 cmos bit 1 output 60 d0 cmos bit 0 (lsb) output 64 or cmos over range 66 sdo spi serial data output 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output exposed paddle avss analog ground pin descriptions - 72 ld qfn, cmos mode (continued) pin number cmos pin name cmos pin function ordering information part number (notes 1, 2) part marking temp. range (c) package (pb-free) pkg. dwg. # isla224p12irz isla224p12 irz -40c to +85c 72 ld qfn l72.10x10e isla224ir72ev1z evaluation board - supports 125/130/200/250 speed grades kmb-001levalz lvds motherboard (interfaces with is la224ir72ev1z operating in lvds output mode) KMB-001CEVALZ cmos motherboard (interfaces with is la224ir72ev1z operating in cmos output mode) notes: 1. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate-e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for isla224p12 . for more information on msl please see techbrief tb363 .
isla224p12 6 fn7983.3 august 17, 2012 table of contents absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 digital specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 switching specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 user initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 temperature calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 over-range indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nap/sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 clock divider synchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 spi physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 spi configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 device configuration/control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 global device configuration/cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 spi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 equivalent circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 a/d evaluation platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 split ground and power planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 clock input considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 exposed paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 bypass and filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 lvds outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 lvcmos outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 unused inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
isla224p12 7 fn7983.3 august 17, 2012 absolute maximum rating s thermal information avdd to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v ovdd to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v avss to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v analog inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v clock inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v logic input to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v logic inputs to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v latchup (tested per jesd-78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 72 ld qfn (notes 3, 4) . . . . . . . . . . . . . . . . 23 0.9 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f sample = 125msps. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol conditions isla224p12 units min (note 5) typ max (note 5) dc specifications (note 6) analog input full-scale analog input range v fs differential 1.95 2.0 2.2 v p-p input resistance r in differential 600 input capacitance c in differential 4.5 pf full scale range temp. drift a vtc full temp 75 ppm/c input offset voltage v os -5.0 -1.7 5.0 mv common-mode output voltage v cm 0.94 v common-mode input current (per pin) i cm 2.6 a/msps clock inputs inputs common mode voltage 0.9 v clkp,clkn input swing 1.8 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 v 1.8v analog supply current i avdd 293 312 ma 1.8v digital supply current (note 6) i ovdd 3ma lvds 75 83 ma power supply rejection ratio psrr 30mhz, 50mv p-p signal on avdd -65 db total power dissipation normal mode p d cmos 590 mw 2ma lvds 640 mw 3ma lvds 662 711 mw nap mode p d 77 85 mw sleep mode p d csb at logic high 6 10 mw
isla224p12 8 fn7983.3 august 17, 2012 nap/sleep mode wakeup time sample clock running 630 s ac specifications differential nonlinearity dnl f in = 105mhz 0.4 lsb integral nonlinearity inl f in = 105mhz 3.0 lsb minimum conversion rate (note 7) f s min 40 msps maximum conversion rate f s max 125 msps signal-to-noise ratio (note 8) snr f in = 30mhz 74.7 dbfs f in = 105mhz 72.7 74.3 dbfs f in = 190mhz 72.9 dbfs f in = 363mhz 70.2 dbfs f in = 461mhz 68.8 dbfs f in = 605mhz 68.0 dbfs signal-to-noise and distortion (note 8) sinad f in = 30mhz 74.2 dbfs f in = 105mhz 70.0 72.8 dbfs f in = 190mhz 71.4 dbfs f in = 363mhz 69.5 dbfs f in = 461mhz 65.7 dbfs f in = 605mhz 60.3 dbfs effective number of bits (note 8) enob f in = 30mhz 12.03 bits f in = 105mhz 11.34 11.80 bits f in = 190mhz 11.57 bits f in = 363mhz 11.25 bits f in = 461mhz 10.62 bits f in = 605mhz 9.72 bits spurious-free dynamic range (note 8) sfdr f in = 30mhz 86 dbc f in = 105mhz 71 79 dbc f in = 190mhz 76 dbc f in = 363mhz 79 dbc f in = 461mhz 70 dbc f in = 605mhz 62 dbc spurious-free dynamic range excluding h2, h3 (note 8) sfdrx23 f in = 30mhz 99 dbc f in = 105mhz 96 dbc f in = 190mhz 92 dbc f in = 363mhz 89 dbc f in = 461mhz 87 dbc f in = 605mhz 83 dbc electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f sample = 125msps. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions isla224p12 units min (note 5) typ max (note 5)
isla224p12 9 fn7983.3 august 17, 2012 intermodulation distortion imd f in = 70mhz -84 dbfs f in = 170mhz -107 dbfs channel-to-channel isolation f in = 10mhz 100 dbfs f in = 121mhz 97 dbfs word error rate wer 10 -12 full power bandwidth fpbw 700 mhz notes: 5. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 6. digital supply current is dependent upon the capacitive loading of the digital outputs. i ovdd specifications apply for 10pf load on each digital output. 7. the dll range setting must be changed for low-speed operation. 8. minimum specification guaranteed when calibrated at +85c. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -1dbfs, f sample = 125msps. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions isla224p12 units min (note 5) typ max (note 5) digital specifications boldface limits apply over the operat ing temperature range, -40c to +85c. parameter symbol conditions min (note 5) typ max (note 5) units inputs input current high (resetn) i ih v in = 1.8v 0 1 10 a input current low (resetn) i il v in = 0v -25 -12 -7 a input current high (sdio) i ih v in = 1.8v 4 12 a input current low (sdio) i il v in = 0v -600 -415 -300 a input voltage high (sdio, resetn) v ih 1.17 v input voltage low (sdio, resetn) v il 0.63 v input current high (clkdiv) (note 9) i ih 16 25 34 a input current low (clkdiv) i il -34 -25 -16 a input capacitance c di 3pf
isla224p12 10 fn7983.3 august 17, 2012 lvds inputs (clkdivrstp, clkdivrstn) input common mode range v icm 825 1575 mv input differential swing (peak-to-peak, single-ended) v id 250 450 mv clkdivrstp input pull-down resistance r ipd 100 k clkdivrstn input pull-up resistance r ipu 100 k lvds outputs differential output voltage (note 10) v t 3ma mode 612 mv p-p output offset voltage v os 3ma mode 1120 1150 1200 mv output rise time t r 240 ps output fall time t f 240 ps cmos outputs voltage output high v oh i oh = -500a ovdd - 0.3 ovdd - 0.1 v voltage output low v ol i ol = 1ma 0.1 0.3 v output rise time t r 1.8 ns output fall time t f 1.4 ns notes: 9. the tri-level inputs internal switching thresholds are approxim ately. 0.43v and 1.34v. it is advised to float the inputs, tie to ground or avdd depending on desired function. 10. the voltage is expressed in peak-to-peak differential swing. the peak-to-peak singled-ended swing is 1/2 of the differential swing. digital specifications boldface limits apply over the operat ing temperature range, -40c to +85c. (continued) parameter symbol conditions min (note 5) typ max (note 5) units timing diagrams figure 3. lvds clkn clkp inp inn t a clkoutn clkoutp t cpd d[13:0]n d[13:0]p latency = l cycles t dc t pd a data n-l b data n-l a data n-l+1 b data n-l+1 b data n-1 a data n b data n
isla224p12 11 fn7983.3 august 17, 2012 figure 4. cmos timing diagrams (continued) clkn clkp inp inn t a clkout t cpd d[13:0] latency = l cycles t dc t pd a data n-l b data n-l a data n-l+1 b data n-l+1 b data n-1 a data n b data n switching specifications boldface limits apply over the operat ing temperature rang e, -40c to +85c. parameter symbol condition min (note 5) typ max (note 5) units adc output aperture delay t a 114 ps rms aperture jitter j a 75 fs input clock to output clock propagation delay t cpd avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c 1.65 2.4 3 ns t cpd avdd, ovdd = 1.8v, t a = +25c 1.9 2.3 2.75 ns relative input clock to output clock propagation delay (note 13) dt cpd avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c -450 450 ps input clock to data propagation delay t pd 1.65 2.4 3.5 ns output clock to data propagation delay, lvds mode t dc rising/falling edge -0.1 0.16 0.5 ns output clock to data propagation delay, cmos mode t dc rising/falling edge -0.1 0.2 0.65 ns synchronous clock divider reset setup time (with respect to the positive edge of clkp) t rsts 0.4 0.06 ns synchronous clock divider reset hold time (with respect to the positive edge of clkp) t rsth 0.02 0.35 ns synchronous clock divider reset recovery time t rstrt dll recovery time after synchronous reset 52 s latency (pipeline delay) l 10 cycles
isla224p12 12 fn7983.3 august 17, 2012 overvoltage recovery t ovr 1cycles spi interface (notes 11, 12) sclk period t clk write operation 16 cycles t clk read operation 16 cycles csb to sclk setup time t s read or write 28 cycles csb after sclk hold time t h write 5 cycles csb after sclk hold time t hr read 16 cycles data valid to sclk setup time t ds write 6 cycles data valid after sclk hold time t dh read or write 4 cycles data valid after sclk time t dvr read 5 cycles notes: 11. spi interface timing is directly proportional to the adc sample period (t s ). values above reflect multiples of a 16ns sample period, and must be scaled proportionally for lower sample rates. adc sample clock must be running for spi communication. 12. the spi may operate asynchronously wi th respect to the adc sample clock. 13. the relative propagation delay is the difference in propagat ion time between any two devices that are matched in temperature and voltage, and is specified over the full operating temperature and voltage range. switching specifications boldface limits apply over the operat ing temperature rang e, -40c to +85c. (continued) parameter symbol condition min (note 5) typ max (note 5) units typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 125msps. figure 5. snr and sfdr vs f in figure 6. hd2 and hd3 vs f in figure 7. snr and sfdr vs a in figure 8. hd2 and hd3 vs a in 60 65 70 75 80 85 90 0 100 200 300 400 500 600 input frequency (mhz) snr snr (dbfs) and sfdr (dbc) sfdr -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 0 100 200 300 400 500 600 input frequency (mhz) hd3 hd2 and hd3 magnitude (dbc) hd2 10 20 30 40 50 60 70 80 90 100 110 -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) sfdr (dbc) snr (dbc) snr and sfdr snr (dbfs) sfdr (dbfs) -110 -100 -90 -80 -70 -60 -50 -40 -30 -60 -50 -40 -30 -20 -10 0 hd2 (dbfs) hd3 (dbc) hd3 (dbfs) input amplitude (dbfs) snr and sfdr hd2 (dbc)
isla224p12 13 fn7983.3 august 17, 2012 figure 9. snr and sfdr vs f sample figure 10. hd2 and hd3 vs f sample figure 11. power vs f sample in 3ma lvds and cmos modes figure 12. differential nonlinearity figure 13. integral nonlinearity figure 14. snr and sfdr vs vcm typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 125msps. (continued) 70 75 80 85 90 40 60 80 100 120 sample rate (msps) sfdr snr snr (dbfs) and sfdr (dbc) -105 -100 -95 -90 -85 -80 -75 40 50 60 70 80 90 100 110 120 sample rate (msps) h2 h3 hd2 and hd3 magnitude (dbc) 425 475 525 575 625 675 40 60 80 100 120 lvds cmos sample rate (msps) total power (mw) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 codes dnl (lsbs) -4 -3 -2 -1 0 1 2 3 4 0 2000 4000 6000 8000 10000 12000 14000 16000 codes inl (lsbs) 60 62 64 66 68 70 72 74 76 78 80 0.75 0.85 0.95 1.05 1.15 input common mode (v) snr (dbfs) and sfdr (dbc)
isla224p12 14 fn7983.3 august 17, 2012 figure 15. noise histogram figure 16. single-tone spectrum @ 105mhz figure 17. single-tone spectrum @ 190mhz figure 18. single-tone spectrum @ 363mhz figure 19. two-tone spectrum (f1 = 70mhz, f2 = 71mhz at -7dbfs) figure 20. two-tone spectrum (f1 = 170mhz, f2 = 171mhz at -7dbfs) typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -1dbfs, f in = 105mhz, f sample = 125msps. (continued) 0 102 2046 19239 65410 76722 6 1 0 10000 20000 30000 40000 50000 60000 70000 80000 90000 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 code stdev = 0.97 lsb number of hits 0 4046 207 32221 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) a in = -1.0 dbfs snr = 74.7 dbfs sfdr = 79.0 dbc sinad = 73.4 dbfs 0 10 20 30 40 50 60 frequency (mhz) amplitude (dbfs) a in = -1.0 dbfs snr = 73.2 dbfs sfdr = 78.2 dbc sinad = 71.6 dbfs -120 -100 -80 -60 -40 -20 0 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) a in = -1.1 dbfs snr = 70.2 dbfs sfdr = 77.1 dbc sinad = 69.4 dbfs 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) imd2 imd3 2nd harmonics 3rd harmonics imd3 =-84dbfs 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude(dbfs) imd2 imd3 2nd harmonics 3rd harmonics imd3 =-107dbfs
isla224p12 15 fn7983.3 august 17, 2012 theory of operation functional description the isla224p12 is based upon a 14-bit, 125msps a/d converter core that utilizes a pipelined successive approximation architecture (see figure 21). the input voltage is captured by a sample-hold amplifier (sha) and converted to a unit of charge. proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive appr oximation operations determine the digital code for each input valu e. digital error correction is also applied, resulting in a total late ncy of 10 clock cycles. this is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. power-on calibration as mentioned previously, the cores perform a self-calibration at start-up. an internal power-on-reset (por) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltag es are above a threshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins must not be connected ? sdo has an internal pull-up and should not be driven externally ? resetn is pulled low by the adc internally during por ? external driving of resetn is optional ? spi communications must not be attempted a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. after the power supply has stabilized, the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. if a subseq uent user-initiated reset is desired, the resetn pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5ma to assure exit from the reset state so calibration can start. the calibration sequence is initiated on the rising edge of resetn, as shown in figure 22. calibration status can be determined by reading the cal_status bit (lsb) at 0xb6. this bit is ?0? during calibration and goes to a logic ?1? when calibration is complete. the data outputs produce 0xcccc during calibration; this can also be used to determine calibration status. while resetn is low, the output clock (clkoutp/clkoutn) is set low. normal operation of the output clock resumes at the next input clock edge (clkp/clkn) after resetn is de-asserted. at 125msps the nominal calibrat ion time is 560ms, while the maximum calibration time is 1000ms. figure 21. a/d core block diagram digital error correction sha 1.25v inp inn clock generation 2.5- bit flash 6- stage 1.5- bit/ stage 3- stage 1-bit/ stage 3- bit flash lvds/lvcmos outputs + ? flash 2.5-bit
isla224p12 16 fn7983.3 august 17, 2012 user initiated reset recalibration of the a/d can be initiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strength in its high impedance state of less than 0.5ma is re commended, as resetn has an internal high impedance pull-up to ovdd. as is the case during power-on reset, resetn and dnc pins must be in the proper state for the calibration to successfully execute. the performance of the isla224p12 changes with variations in temperature, supply voltage or sample rate. the extent of these changes may necessitate recalibr ation, depending on system performance requirements. best performance will be achieved by recalibrating the a/d under th e environmental conditions at which it will operate. a supply voltage variation of <100mv will generally result in an snr change of <0. 5dbfs and sfdr change of <3dbc. in situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. reducing the sample rate by less than 80msps will typically result in an snr change of <0 .5dbfs and an sfdr change of <3dbc. figures 23 through 28 show the effect of temperature on snr and sfdr performance with power on calibration performed at -40c, +25c, and +85c. each plot shows the variation of snr/sfdr across temperature after a single power on calibration at -40c, +25c an d +85c. best performance is typically achieved by a user-initi ated power on ca libration at the operating conditions, as stated earlier. however, it can be seen that performance drift with temp erature is not a very strong function of the temperature at wh ich the power on calibration is performed. figure 22. calibration timing clkp clkn clkoutp calibration begins calibration complete calibration time resetn cal_status bit temperature calibration figure 23. typical snr perf ormance vs temperature, device calibrated at -40 c , f in = 105mhz figure 24. typical sfdr pe rformance vs temperature, device calibrated at -40 c , f in = 105mhz figure 25. typical snr perf ormance vs temperature, device calibrated at +25 c , f in = 105mhz figure 26. typical sfdr performance vs temperature, device calibrated at +25 c , f in = 105mhz 73.50 73.75 74.00 74.25 74.50 74.75 75.00 -40 -35 -30 -25 -20 temperature (c) snr (dbfs) -2dbfs analog input -1dbfs analog input 75 80 85 -40 -35 -30 -25 -20 sfdr (dbc) -2dbfs analog input -1dbfs analog input temperature (c) 73.50 73.75 74.00 74.25 74.50 74.75 75.00 5 1015202530354045 snr (dbfs) temperature (c) -2dbfs analog input -1dbfs analog input 75 80 85 5 1015202530354045 sfdr (dbc) -2dbfs analog input -1dbfs analog input temperature (c)
isla224p12 17 fn7983.3 august 17, 2012 analog input a single fully differential inpu t (vinp/vinn) connects to the sample and hold amplifier (sha) of each unit a/d. the ideal full-scale input voltage is 2.0v, centered at the vcm voltage of 0.94v, as shown in figure 29. best performance is obtained when the analog inputs are driven differentially. the common-mode ou tput voltage, vcm, should be used to properly bias the inputs, as shown in figures 30 through 32. an rf transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in figures 30 and 31. this dual transformer scheme is used to improve common-mode rejection, which keeps the co mmon-mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differential input resistance of the isla224p12 is 600 ? . the sha design uses a switched capacitor input stage (see figure 45), which creates current spikes when the sampling capacitance is reconnected to th e input voltage. this causes a disturbance at the input, which must settle before the next sampling point. lower source impedance will result in faster settling and improved performance. therefore a 2:1 or 1:1 transformer and low shunt resi stance are recommended for optimal performance. a differential amplifier, as show n in the simplified block diagram in figure 32, can be used in applications that require dc-coupling. in this configuratio n, the amplifier will typically dominate the achievable snr and distortion performance. intersil?s new isl552xx differential amplifier family can also be used in certain ac applications with minimal performance degradation. contac t the factory for more information. figure 27. typical snr performance vs temperature, device calibrated at +85 c , f in = 105mhz figure 28. typical sfdr performance vs temperature, device calibrated at +85 c , f in = 105mhz temperature calibration (continued) 73.50 73.75 74.00 74.25 74.50 74.75 75.00 65 70 75 80 85 snr (dbfs) temperature (c) -2dbfs analog input -1dbfs analog input 75 80 85 65 70 75 80 85 sfdr (dbc) -2dbfs analog input -1dbfs analog input temperature (c) figure 29. analog input range 1.0 1.8 0.6 0.2 1.4 vinp vinn vcm 0.94v 1.0v figure 30. transformer input for general purpose applications adt1-1wt 0.1f a/d vcm adt1-1wt 1000pf figure 31. transmission-line transformer input for high if applications a/d vcm 1000pf 1000pf tx-2-5-1 adtl1-12 figure 32. differential amplifier input a/d
isla224p12 18 fn7983.3 august 17, 2012 clock input the clock input circuit is a differential pair (see figure 46). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 impedance ratio will provide increased drive levels. the clock input is functional with ac-coupled lvds, lvpecl, and cml drive levels. to maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. the recommended drive circuit is shown in figure 33. a duty range of 40% to 60% is accept able. the clock can be driven single-ended, but this will reduce the edge rate and may impact snr performance. the clock inputs are internally self-biased to avdd/2 to facilitate ac-coupling. a selectable 2x or 4x frequency divider is provided in series with the clock input. the divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate or in 4x mode with a sample clock equa l to four times the desired sample rate. this allows the use of the phase slip feature, which enables synchronization of multip le adcs. the phase slip feature can be used as an alternative to using the clkdivrst pins to synchronize adcs in a multiple adc system. the clock divider can also be controlled through the spi port, which overrides the clkdiv pin setting. see ?spi physical interface? on page 22. a delay-locked loop (dll) generates internal clock signals for vari ous stages within the charge pipeline. if the frequency of the input clock changes, the dll may take up to 100 s to regain lock at 125msps. the lock time is inversely proportional to the sample rate. the dll has two ranges of operation; slow and fast. the slow range can be used for sample rates between 40msps and 100msps, while the default fast range can be used from 80msps to the maximum specified sample rate. jitter in a sampled data system, cloc k jitter directly impacts the achievable snr performance. the theoretical relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 34. this relationship shows the snr that would be achieved if clock jitter were the only non-ideal factor. in reality, achievable snr is limited by internal factors, such as linearity, aperture jitter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in figure 3. the internal aperture jitter combines with the input clock jitt er in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. voltage reference a temperature compensated internal voltage reference provides the reference charges used in the successive approximation operations. the full-scale range of each a/d is proportional to the reference voltage. the nominal value of the voltage reference is 1.25v. digital outputs output data is available as a parallel bus in lvds-compatible (default) or cmos modes. in either case, the data is presented in double data rate (ddr) format. figures 3 and 4 show the timing relationships for lvds and cmos modes, respectively. additionally, the drive current for lvds mode can be set to a nominal 3ma (default) or a power-saving 2ma. the lower current setting can be used in designs where the receiver is in close physical proximity to the a/d. the applicability of this setting is dependent upon the pcb layout, therefore the user should experiment to determine if performance degradation is observed. the output mode can be controlled through the spi port, by writing to address 0x73, see ?serial peripheral interface? on page 22. an external resistor creates the bias for the lvds drivers. a 10k ? , 1% resistor must be connected from the rlvds pin to ovss. table 1. clkdiv pin settings clkdiv pin divide ratio avss 2 float 1 avdd 4 figure 33. recommended clock drive tc4-19g2+ 1000pf 1000pf clkp clkn 0.01f 200 1000pf nr 20 log 10 1 2 f in t j ------------------- - ?? ?? = (eq. 1) figure 34. snr vs clock jitter tj = 100ps tj = 10ps tj = 1ps tj = 0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1m 10m 100m 1g snr (db) input frequency (hz)
isla224p12 19 fn7983.3 august 17, 2012 over-range indicator the over-range (or) bit is asserted when the output code reaches positive full-scale (e.g. 0xfff in offset binary mode). the output code does not wrap around during an over-range condition. the or bit is updated at the sample rate. power dissipation the power dissipated by the isla224p12 is primarily dependent on the sample rate and the output modes: lvds vs cmos and ddr vs sdr. there is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. the output supply dissipation changes to a lesser degree in lvds mode, but is more strongly related to the clock frequency in cmos mode. nap/sleep portions of the device may be shut down to save power during times when operation of the a/d is not required. two power saving modes are available: nap, and sleep. nap mode reduces power dissipation to <103mw while sleep mode reduces power dissipation to <19mw. all digital outputs (data, clkout and or) are placed in a high impedance state during nap or sleep. the input clock should remain running and at a fixed frequency during nap or sleep, and csb should be high. recovery time from nap mode will increase if the clock is stopped, since the internal dll can take up to 104s to regain lock at 125msps. by default after the device is powered on, the operational state is controlled by the napslp pin as shown in table 2. the power-down mode can also be controlled through the spi port, which overrides the napslp pin setting. details on this are contained in ?serial peripheral interface? on page 22. data format output data can be presented in three formats: two?s complement(default), gray code and offset binary. the data format can also be controlled through the spi port, by writing to address 0x73. details on this are contained in ?serial peripheral interface? on page 22. offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the mo st positive input to 0xfff (all ones). two?s complement coding simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 35 shows this operation. converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 36. mapping of the input voltage to the various data formats is shown in table 3. clock divider synchronous reset an output clock (clkoutp, clkoutn) is provided to facilitate latching of the sampled data. the output cloc k frequency is equal to the input clock frequency divided by the internal clock divider setting (see ?clock input? on page 18). table 2. napslp pin settings napslp pin mode avss normal float sleep avdd nap table 3. input voltage to output code mapping input voltage offset binary two?s complement gray code ?full scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 ?full scale + 1lsb 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 mid?scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 +full scale ? 1lsb 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 +full scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 figure 35. binary to gray code conversion 12 13 11 0 1 binary 12 13 11 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 figure 36. gray code to binary conversion 12 13 11 0 1 binary 12 13 11 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ?
isla224p12 20 fn7983.3 august 17, 2012 for clock divide settings > ?1?, the absolute phase of the output clocks for multiple a/ds is indeterminate - there will be a phase ambiguity between the output cloc ks of adcs in a multiple adc system. the clkdivrst feature allows the phase of multiple a/ds to be synchronized (see figure 37) when the internal clock divider is used, greatly simplifying data capture in systems employing multiple a/ds. for clock divide setting = ?1?, there is no phase ambiguity between clock outputs in a multiple adc system and clkdivrst can be left as a dnc (do not connect) the clkdivrst signal must be we ll-timed with respect to the sample clock (see ?switching specifications? on page 11). figure 37 shows assertion of clkdivrstp by a positive edge (clkdivrstn must be driven but is not shown); clkdivrstp can remain high indefinitely after a synchronization event. clkdivrstp can also be a pulse if needed, with clkdivrstp returning to a logic ?0? after assertion; in this case the clkdivrst pulse width should be a minimum of 3 input sample clock periods. in applications where multiple clkdivrst pulse events are required, a user should wait a minimum of 30 clock cycles before starting a second clkdivrst pulse event. it will take a maximum of 30 input clock cycles to attain synchronization (t rstrt ) in applications where the input clock is not interrupted; if the input clock is interrupted clkout will be static or indeterminate until synchronization is attained. in some applications, interruptin g the input sample clock briefly (~ 150 cycles max) can simplify the timing requirements for synchronization using clkdivrst), in this case the total clkdivrst recovery time will increase by the number of input clock cycles the sample clock is held static. valid data is available (after recovery) in al l cases after the normal pipeline latency. intersil application note 1604 describes the synchronization of multiple isla1xxp50s. this docu ment discusses the topic of synchronization in more detail and can be used to better understand the isla2xxpxx adcs? operation. figure 37. synchronous reset operation s1 s2 s0 s3 s1 s2 s0 s3 clkdivrstp adc1 output data adc1 clkoutp adc2 clkoutp (phase 1) adc2 clkoutp (phase 2) s1 l+t d t rsth t rsts t rstrt adc2 output data analog input sample clock input (clkdiv = 2) s2 notes: 14. delay equals fixed pipeline latency (l cycles) plus fixed analog propagation delay td. 15. clkdivrstp setup and hold times are with respect to input sample clock rising edge. clkdivrstn is not shown, but must be driven, and is the compliment of clkdivrstp. 16. either output clock phase (phase 1 or phas e 2 ) equally likely prior to synchronization. (note 16) (note 15) (note 15) (note 14)
isla224p12 21 fn7983.3 august 17, 2012 figure 38. msb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a10 figure 39. lsb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a2 figure 40. spi write t s t hi t clk t lo r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t h t dhw t dsw spi write csb sclk sdio figure 41. spi read ( 3 wire mode ) (4 wire mode) w1 w 0 a12 a9 a2 a1 d7 d6 d3 d2 d1 d7 d3 d2 d1 d0 a0 writing a read command reading data d0 t hr t dvr spi read t hi t clk t lo t dhw t dsw t s csb sclk sdio sdo a11 a10 r/w
isla224p12 22 fn7983.3 august 17, 2012 serial peripheral interface a serial peripheral interface (spi) bus is used to facilitate configuration of the device and to optimize performance. the spi bus consists of chip select (csb), serial clock (sclk) serial data output (sdo), and serial data input/output (sdio). the maximum sclk rate is equal to the a/d sample rate (f sample ) divided by 16 for both write operations and read operations. at f sample = 125mhz, maximum sclk is 7.8125mhz for writing and read operations. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust perfor mance or functional parameters. many registers in the available address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined values within defined registers are reserved and should not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the serial clock pin (sclk) provid es synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin in three-wire mode. the state of the sdio pin is set automatically in the communication protocol (described in the following). a dedicated serial data output pin (sdo) can be activated by setting 0x00[7] high to allow operation in four-wire mode. the spi port operates in a half duplex master/slave configuration, with the isla224p12 functioning as a slave. multiple slave devices can inte rface to a single master in three-wire mode only, since the sdo output of an unaddressed device is asserted in four wire mode. the chip-select bar (csb) pin determines when a slave device is being addressed. multiple slav e devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three- wire mode). if multiple slave devices are selected for reading at the same time, the results will be indeterminate. the communication protocol begins with an instruction/address phase. the first rising sclk edge following a high-to-low transition on csb determines the beginning of the two-byte instruction/address command; sclk must be static low before the csb transition. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figure s 38 and 39 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode, the address is incremented for multi-byte transfers, while in lsb-fi rst mode it?s decremented. in the default mode, the msb is r/w, which determines if the data is to be read (active high) or written. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see table 4). the lower 13 bits contain the first address for the data transfer. this relationship is illustrated in figure 40, and timing values are given in ?switching specifications? on page 11. after the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the a/d (based on the r/w bit status). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. for transfers of four bytes or more, csb is allowed to stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point, the stat e machine will reset and terminate the data transfer. figure 42. 2-byte transfer csb sclk sdio instruction/address data word 1 data word 2 csb stalling figure 43. n-byte transfer csb sclk sdio instruction/address data word 1 data word n last legal csb stalling table 4. byte transfer selection [w1:w0] bytes transferred 00 1 01 2
isla224p12 23 fn7983.3 august 17, 2012 figures 42 and 43 illustrate the timing relationships for 2-byte and n-byte transfers, respective ly. the operation for a 3-byte transfer can be inferred from these diagrams. spi configuration address 0x00: chip_port_config bit ordering and spi reset are contro lled by this register. bit order can be selected as msb to lsb (m sb first) or lsb to msb (lsb first) to accommodate various micro controllers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to interpret serial data as arriving in lsb to msb order. bit 5 soft reset setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. address 0x02: burst_end if a series of sequential register s are to be set, burst mode can improve throughput by eliminating redundant addressing. the burst is ended by pulling the csb pin high. setting the burst_end address determines the end of the transfer. during a write operation, the user must be ca utious to transm it the correct number of bytes based on the starting and en ding addresses. bits 7:0 burst end address this register value determines the ending address of the burst data. device information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, respectively, can be read from these two registers. device configuration/control a common spi map, which can ac commodate single-channel or multi-channel devices, is used for all intersil a/d products. address 0x20: offset_coarse_adc0 address 0x21: offset_fine_adc0 the input offset of the a/d core can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 5. the data format is twos complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x20 and 0x21 to be used by the adc (see description for 0xfe). address 0x22: gain_coarse_adc0 address 0x23: gain_medium_adc0 address 0x24: gain_fine_adc0 gain of the a/d core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. (?0011? @ -4.2% and ?1100? @ +4.2%) it is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 0x0023 and 0x24. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x23 and 0x24 to be used by the adc (see description for 0xfe). 10 3 11 4 or more table 4. byte transfer selection (continued) [w1:w0] bytes transferred table 5. offset adjustments parameter 0x20[7:0] coarse offset 0x21[7:0] fine offset steps 255 255 ?full scale (0x00) -133lsb (-47mv) -5lsb (-1.75mv) mid?scale (0x80) 0.0lsb (0.0mv) 0.0lsb +full scale (0xff) +133lsb (+47mv) +5lsb (+1.75mv) nominal step size 1.04lsb (0.37mv) 0.04lsb (0.014mv) table 6. coarse gain adjustment 0x22[3:0] core 0 0x26[3:0] core 1 nominal coarse gain adjust (%) bit3 +2.8 bit2 +1.4 bit1 -2.8 bit0 -1.4
isla224p12 24 fn7983.3 august 17, 2012 address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level napslp pin can sele ct normal operation, nap or sleep modes (refer to?nap/sleep? on page 19). this functionality can be overridden and controlled through the spi. this is an indexed function when controlled from the spi, but a global function when driven from the pin. this register is not changed by a soft reset. address 0x26: offset_coarse_adc1 address 0x27: offset_fine_adc1 the input offset of a/d core #1 can be adjusted in fine and coarse steps in the same way that offset for core #0 can be adjusted. both adjustments are made via an 8-bit word as detailed in table 5. the data format is two?s complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x26 and 0x27 to be used by the adc (see description for 0xfe). address 0x28: gain_coarse_adc1 address 0x29: gain_medium_adc1 address 0x2a: gain_fine_adc1 gain of a/d core #1 can be adjusted in coarse, medium and fine steps in the same way that core #0 can be adjusted. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. bit 0 in register 0xfe must be se t high to enable updates written to 0x29 and 0x2a to be used by the adc (see description for 0xfe). global device configuration/control address 0x71: phase_slip the output data clock is generated by dividing down the a/d input sample clock. some systems with multiple a/ds can more easily latch the data from each a/d by controlling the phase of the output data clock. this co ntrol is accomplished through the use of the phase_slip spi feature, which allows the rising edge of the output data clock to be advanced by one input clock period, as shown in the figure 44. the clock divider (clkdiv>=2) is required to use phase_slip. execution of a phase_slip command is accomplished by first wr iting a '0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address 0x71. address 0x72: clock_divide the isla224p12 has a selectable cl ock divider that can be set to divide by four, two or one (no divi sion). by default, the tri-level clkdiv pin selects the diviso r this functionality can be overridden and controlled through the spi, as shown in table 9. this register is not changed by a soft reset. address 0x73: output_mode_a the output_mode_a register controls the physical output format of the data, as well as the logi cal coding. the isla224p12 can present output data in two physical formats: lvds(default) or lvcmos. additionally, the drive strength in lvds mode can be set high (default, 3ma or low (2ma). data can be coded in three possible formats: two?s complement (default), gray code or offset binary. see table 11. table 7. medium and fine gain adjustments parameter 0x23[7:0] medium gain 0x24[7:0] fine gain steps 256 256 ?full scale (0x00) -2% -0.20% mid?scale (0x80) 0.00% 0.00% +full scale (0xff) +2% +0.2% nominal step size 0.016% 0.0016% table 8. power-down control value 0x25[2:0] power down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode table 9. clock divider selection value 0x72[2:0] clock divider 000 pin control 001 divide by 1 010 divide by 2 100 divide by 4 other not allowed figure 44. phase slip adc input clock (250mhz) output data clock (125mhz) no clock_slip output data clock (125mhz) 1 clock_slip output data clock (125mhz) 2 clock_slip 4ns 8ns 4ns clkdiv=2
isla224p12 25 fn7983.3 august 17, 2012 this register is not changed by a soft reset. address 0x74: output_mode_b bit 6 dll range this bit sets the dll operating range to fast (default) or slow. internal clock signals are generate d by a delay-locked loop (dll), which has a finite operating range. table 12 shows the allowable sample rate ranges for the slow and fast settings. address 0xb6: calibration status the lsb at address 0xb6 can be read to determine calibration status. the bit is ?0? during calibration and goes to a logic ?1? when calibration is complete. this register is unique in that it can be read after por at calibration, unlike the other registers on chip, which can?t be read until calibration is complete. device test the isla224p12 can produce preset or user defined patterns on the digital outputs to facilitate in -situ testing. a user can pick from preset built-in patterns by writing to the output test mode field [7:4] at 0xc0 or user defined patterns by writing to the user test mode field [2:0] at 0xc0. the user defined patterns should be loaded at addre ss space 0xc1 through 0xd0, see the ?spi memory map? on page 27 for more detail. the predefined patterns are shown in table 13. the test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. address 0xc0: test_io bits 7:4 output test mode these bits set the test mode according to table 13. other values are reserved. user test patterns loaded at 0xc1 through 0xd0 are also available by writing ?1000? to [7:4] at 0xc0 and a pattern depth value to [2:0] at 0xc0. see the ?spi memory map? on page 27. bits 2:0 user test mode the three lsbs in this register determine the test pattern in combination with registers 0xc1 through 0xd0. refer to the ?spi memory map? on page 27. address 0xc1: user_patt1_lsb address 0xc2: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 1. address 0xc3: user_patt2_lsb address 0xc4: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 2 address 0xc5: user_patt3_lsb address 0xc6: user_patt3_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 3 address 0xc7: user_patt4_lsb address 0xc8: user_patt4_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 4. address 0xc9: user_patt5_lsb address 0xca: user_patt5_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 5. table 10. output mode control value 0x73[7:5] output mode 000 lvds 3ma (default) 001 lvds 2ma 100 lvcmos table 11. output format control value 0x73[2:0] output format 000 two?s complement (default) 010 gray code 100 offset binary table 12. dll ranges dll range min max unit slow 40 100 msps fast 80 125 msps table 13. output test modes value 0xc0[7:4] output test mode word 1 word 2 0000 off 0001 midscale 0x8000 n/a 0010 positive full-scale 0xffff n/a 0011 negative full-scale 0x0000 n/a 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 reserved n/a n/a 0111 reserved 1000 user pattern user_patt1 user_patt2 1001 reserved n/a n/a 1010 ramp n/a n/a
isla224p12 26 fn7983.3 august 17, 2012 address 0xcb: user_patt6_lsb address 0xcc: user_patt6_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 6 address 0xcd: user_patt7_lsb address 0xce: user_patt7_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 7. address 0xcf: user_patt8_lsb address 0xd0: user_patt8_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 8. address 0xfe: offset/gain_adjust_enable bit 0 at this register must be se t high to enable adjustment of offset coarse and fine adjustments adc0 (0x20 and 0x21), adc1 (0x26 and 0x27) and gain medium and gain fine adjustments adc0 (0x23 and 0x24), adc1 (0x29 and 0x2a). it is recommended that new data be wr itten to the offset and gain adjustment registers adc0(0x20, 0x21, 0x23, 0x24) and adc1(0x26, 0x27, 0x29, 0x2a) while bit 0 is a ?0?. subsequently, bit 0 should be set to ?1? to allow the values written to the aforementioned registers to be used by the adc. bit 0 should be set to a ?0? upon completion
isla224p12 27 fn7983.3 august 17, 2012 spi memory map addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) spi config/control 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h 01 reserved reserved 02 burst_end burst end address [7:0] 00h 03-07 reserved reserved dut info 08 chip_id chip id # read only 09 chip_version chip version # read only 0a-0f reserved reserved device config/control 10-1f reserved reserved 20 offset_coarse_adc0 coarse offset cal. value 21 offset_fine_adc0 fine offset cal. value 22 gain_coarse_adc0 reserved coarse gain cal. value 23 gain_medium_adc0 medium gain cal. value 24 gain_fine_adc0 fine gain cal. value 25 modes_adc0 reserved power down mode adc0 [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not reset by soft reset 26 offset_coarse_adc1 coarse offset cal. value 27 offset_fine_adc1 fine offset cal. value 28 gain_coarse_adc1 reserved coarse gain cal. value 29 gain_medium_adc1 medium gain cal. value 2a gain_fine_adc1 fine gain cal. value 2b modes_adc1 reserved power down mode adc1 [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not reset by soft reset 2c-2f reserved reserved 33-4a reserved reserved 4b reserved reserved read only 4c reserved reserved read only 4d reserved enable pd reset divider [2:0] select 00h 4e-6f reserved reserved 70 skew_diff differential skew 80h 71 phase_slip reserved next clock edge 00h 72 clock_divide clock divide [2:0] 000 = pin control 001 = divide by 1 010 = divide by 2 100 = divide by 4 other codes = reserved 00h not reset by soft reset
isla224p12 28 fn7983.3 august 17, 2012 device config/control 73 output_mode_a output mode [7:5] 000 = lvds 3ma (default) 001 = lvds 2ma 100 = lvcmos other codes = reserved output format [2:0] 000 = two?s complement (default) 010 = gray code 100 = offset binary other codes = reserved 00h not reset by soft reset 74 output_mode_b dll range 0 = fast 1 = slow default=?0 ? 00h not reset by soft reset 75-b5 reserved reserved b6 cal_status calibration done read only b7-bf reserved device test c0 test_io output test mode [7:4] user test mode [2:0] 0 = user pattern 1-2 1 = cycle pattern 1 through 4 2 = cycle pattern 1 through 6 3 = cycle pattern 1 through 8 4-7 = na 00h 0 = off (note 14) 1 = midscale short 2 = +fs short 3 = -fs short 4 = checkerboard (note 15) 5-6 = reserved 7 = all on/ off (note 16) 8 = user pattern (1 to 8 deep) 9 = reserved 10 = ramp 11-15 = reserved c1 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 c2 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c3 user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c4 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c5 user_patt3_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c6 user_patt3_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c7 user_patt4_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c8 user_patt4_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c9 user_patt5_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h ca user_patt5_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cb user_patt6_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h cc user_patt6_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cd user_patt7_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h ce user_patt7_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cf user_patt8_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h d0 user_patt8_msb b15 b14 b13 b12 b11 b10 b9 b8 00h d1-fd reserved reserved fe offset/gain_adjust_enable enable ?1?=enable 00h ff reserved notes: 14. during calibration xcccc (msb justified) is presented at the ou tput data bus, toggling on the lsb (and higher) data bits occ urs at completion of calibration. this behavior can be used as an option to determine calibration state. 15. use test_io = 0x41 for checkerboard outputs on ddr outputs. 16. use test_io = 0x71 for all ones/zeroes outputs on ddr outputs. spi memory map (continued) addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex)
isla224p12 29 fn7983.3 august 17, 2012 equivalent circuits figure 45. analog inputs figure 46. clock inputs figure 47. tri-level digital inputs figure 48. digital inputs figure 49. lvds outputs figure 50. cmos outputs avdd inp inn avdd csamp 4pf csamp 4pf to charge pipeline to charge pipeline e1 e3 e3 e2 e2 e1 600 avdd clkp clkn avdd avdd to clock-phase generation avdd 11k 18k 11k 18k avdd input avdd avdd avdd to sense logic 75k 75k 75k 75k 280 input ovdd ovdd 280 to logic 20k ovdd (20k pull-up on resetn only) d[13:0]p ovdd ovdd 2ma or 3ma 2ma or 3ma data data data data d[13:0]n ovdd d[13:0] ovdd ovdd data
isla224p12 30 fn7983.3 august 17, 2012 a/d evaluation platform intersil offers an a/d evaluation platform, which can be used to evaluate any of intersil?s high speed a/d products. the platform consists of a fpga based data capture motherboard and a family of a/d daughtercards. this usb based platform allows a user to quickly evaluate the a/d?s performance at a user?s specific application frequency requirem ents. more information is available at http://www.intersil.com/converters/adc_eval_platform/ layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer inputs for the analog input and clock signals. locate transformers and terminations as close to the chip as possible. exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for op timal thermal performance. bypass and filtering bulk capacitors should have lo w equivalent series resistance. tantalum is a good choice. for best performance, keep ceramic bypass capacitors very close to device pins. longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. make sure that connections to ground are direct and low impedance. avoid forming ground loops. lvds outputs output traces and connections mu st be designed for 50w (100w differential) characteristic impe dance. keep traces direct and minimize bends wher e possible. avoid crossing ground and power-plane breaks with signal traces. lvcmos outputs output traces and connections must be designed for 50w characteristic impedance. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) that will not be operated do not require co nnection to ensure optimal a/d performance. these inputs can be left floating if they are not used. tri-level inputs (napslp) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. definitions analog input bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by fft analysis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time required after the rise of the clock input for the sa mpling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-dist ortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02 gain error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less than 2 lsb. it is typically expressed in percent. i2e the intersil interleave engine. this highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. integral non-linearity (inl) is the maximum deviation of the a/d?s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. figure 51. vcm_out output equivalent circuits (continued) vcm avdd 0.94v + ?
isla224p12 31 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7983.3 august 17, 2012 for additional products, see www.intersil.com/product_tree least significant bit (lsb) is the bit that has the smallest value or weight in a digital word. its value in terms of input voltage is v fs /(2 n -1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the a/d output. thes e codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion and th e appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of the observed magnitude of a spur in the a/d fft, caused by an ac signal superimposed on the power supply voltage. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of db when the power of the fundamental is used as the reference, or dbfs (db to full scale) when the converter?s full-scale input power is used as the reference. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the largest spurious spectral component. the largest spurious spectral component may or may not be a harmonic. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isla224p12 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change july 12, 2012 fn7983.3 features: remove d duplicate ?nap and sleep modes?. june 26, 2012 fn7983.2 initial release
isla224p12 32 fn7983.3 august 17, 2012 package outline drawing l72.10x10e 72 lead quad flat no-lead plastic package rev 0, 11/09 72 exposed 1 8.500 ref. (4x) 6.000 ref. 7.150 ref. 4.150 ref. 3.000 0.100 a mc b a 0.100 m c b 6 pin #1 index area pad area ref. located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.10 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to ansi y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "z" side view typical recommended land pattern top view 1 72 y 72 1 z r0.115 typ. r0.200 seating plane r0.200 max. all around 10.00 0.10 0.500 0.100 c0.190x45 (0.350) (1.500) 0.450 0.190~0.245 0.650 0.050 0.025 0.020 0.23 0.050 0.50 0.85 0.050 11 9.75 0.10 c 9.75 (4x) 0.15 index area 6 pin 1 10.00 a b 10.00 9.75 all around (4x 9.70) (4.15 ref) (4x 8.50) ( 72x 0 .23) ( 72x 0 .70) (7.15) (6.00) (3.00 ) c0.400x45 (4x) ( 0 . 1 2 5 a l l a r o u n d ) x a 0.100 c mb 0.050 m c c 0.080 0.100 c detail "x" detail "y" angular 2.50 package outline compliant to jesd-m0220. 7.

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